This invention relates generally to the field of optical lithography, and more particularly, to a method for incorporating inter-layer constraints in an Model Based Optical Proximity Correction (MBOPC) software tool for use in an optical lithography system, to provide accurate correction of the device shapes in a photo-mask that fulfill required performance criteria for the resulting Very Large Scale Integrated (VLSI) circuit.
The optical micro-lithography process in semiconductor fabrication, also known as the photolithography process, consists of duplicating desired circuit patterns onto semiconductor wafers for an overall desired circuit performance. The desired circuit patterns are typically represented as opaque, complete and semi-transparent regions on a template commonly referred to as a photomask. In optical micro-lithography, patterns on the photo-mask template are projected onto the photo-resist coated wafer by way of optical imaging through an exposure system.
The continuous advancement of VLSI chip manufacturing technology to meet Moore's law of shrinking device dimensions in geometric progression has spurred the development of Resolution Enhancement Techniques (RET) and Optical Proximity Correction (OPC) methodologies in optical microlithography. The latter is the method of choice for chip manufacturers for the foreseeable future due to its high volume yield in manufacturing and past history of success. However, the ever shrinking device dimensions combined with the desire to enhance circuit performance in the deep sub-wavelength domain makes it increasingly more difficult for complex OPC methodologies to achieve high fidelity of mask patterns while also ensuring proper circuit performance on the printed wafer.
A Very Large Scale Integrated (VLSI) circuit consists of several patterned physical layers of material on top of one-another on a wafer, fabricated as patterned shapes on a wafer. In a typical VLSI Circuit, the bottom-most layer of a circuit consists of the diffusion layer (RX) which creates the source and the drain regions of the Complimentary Metal Oxide Silicon Field Effect Transistors (CMOS-FET, or CMOS). The layer above RX consists of a poly-silicon (PC) layer. The regions of PC layers that overlap the RX regions are called the gate regions and the rest of the PC layers connect several CMOS transistors. The source, drain and the gate regions are connected by contact pads (CA) to several layers of metal interconnects (Mx, for x=1, 2, 3, . . . ). Each layer of metal is connected to the metal layer above by a via layer (Vx, for x=1, 2, 3, . . . ). In the current art, there can be a score of metal and via layers in the final VLSI circuit.
The lithographic process used to form a given physical layer on the wafer includes designing one or more mask shape layouts used to transfer the circuit design shapes to the wafer. Optical proximity correction (OPC) is a process used to optimize the shapes on the mask so that the transfer of mask patterns to the physical layer reproduces the desired circuit design shapes with optimal fidelity. Typically the lithographic process for each physical layer is considered independently of the other physical layers.
Current OPC algorithms pre-correct the mask shapes by segmenting the shape edges and shifting the position of the segments by small amounts. In the current state of the art, Model-Based OPC (MBOPC) software emulates the physical and optical effects that are mostly responsible for the non-fidelity of mask shapes printed on the wafer, as will be described hereinafter with reference to FIG. 1. In the correction phase of MBOPC, the mask shapes are iteratively modified so that the shapes printed on the wafer match the desired shape as closely as possible. This method automatically deforms existing mask shapes to achieve the target dimensions on the wafer. However, the current art can not objectively incorporate and satisfy the proper functioning of the circuit.
The aforementioned methodology for single layer MBOPC is illustrated in FIG. 1. In the current state of the art, an input mask layout 101 and a target image 106 are provided. The mask shapes are divided into segments to form segmented mask shapes 103, where each segment is typically provided with a self-contained evaluation points at which values of the mask image will be computed. The optical and the resist image are then evaluated at evaluation points (Block 104). The images at each of the evaluation points are then checked (Block 105) against the target image 106 to ensure the simulated image is within predetermined tolerances. Stated another way, the deviation of the edges of simulated mask image with respect to the edges of the target image, referred to as Edge Placement Errors (EPEs), should be within predetermined tolerances. Here, an edge of an image shape may be defined by the image intensity contour that equals or exceeds the dose-to-clear value for the lithographic process, and depends on the type of resist used. Typically, EPE tolerances are expressed as geometric rules or constraints on the image shapes relative to shapes on the same physical layer. If the image does not remain within tolerance or the allowable EPE, the segment is iteratively moved forward or backward 107 until all of the simulated image edges are located within an accepted tolerance of the location of the target image edges. Eventually, the final corrected mask layout is outputted 108.
For the proper functioning of the circuit, it is important that each layer overlaps the following layer in the proper region and their overlapping area satisfy certain tolerance criteria. For example, it may be more important for proper functioning of the circuit that the contact layers and the metal layers overlap properly at the circuit level and that they have sufficient overlap regions, whereas the specific location of the edges of such overlapped regions may not be as critical.
In the current art of MBOPC, the mask is corrected in such a way that only one layer can be fabricated according to the specifications. Though it is important that each layer is fabricated to its individual specifications, it is equally important to ensure that the inter-layer specifications are also satisfied.
In view of the above, there is a need for an OPC methodology that considers proper functioning of the interacting circuit layers, for example, by considering overlapping shapes among the layers of the circuit.